Clock Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
6.3

Clock Mode

Table 6.2 indicates the input/output clock frequency. Table 6.3 shows the usable frequency ranges.
Table 6.2 Input/Output Clock Frequency
Mode
MD_CLK
Pin Setting
0 0
1 1
In clock mode 0, the clock signal is the input from the EXTAL pin or the crystal oscillator. The PLL circuit shapes
waveforms and multiples the frequency, and then supplies the clock to the LSI. The oscillating frequency for the crystal
resonator and EXTAL pin input clock ranges from 10 to 13.33 MHz. The frequency range of CKIO is from 50 to 66.67
MHz.
In clock mode 1, the clock signal is the input from the USB_X1 pin or the crystal oscillator. The PLL circuit shapes
waveforms and multiples the frequency, and then supplies the clock to the LSI. The oscillating frequency for the crystal
resonator and USB_X1 pin input clock is 48 MHz. The frequency of CKIO is 64 MHz.
When changing the frequency, be sure to set the standby_mode_en bit of the power control register in the PL310. For
details on the register, see CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual issued by Arm Ltd.
After the setting of IFC[1:0] in the frequency control register is changed, the hardware automatically stops the bus master
and starts changing the frequency following the wait for completion of the issuing-finished request from the bus master.
Since processing to change the frequency cannot start if completion of the issuing-finished request is not possible at this
time, do not proceed with access to the registers of modules in the module-standby state and so on. Furthermore, as the
issuing of unintended requests by the bus master is inhibited, using software to stop all bus masters in preparation for
proceeding to change the frequency is also effective.
Table 6.3 Settable Frequency Ranges
PLL
Frequency
Multiplier
FRQCR
Setting
*1
Mode PLL Circuit
0 H'x035 ON (× 30)
H'x135
H'x335
1 H'x035 ON (× 32)
H'x135
H'x335
Note 1. x in the FRQCR register setting depends on the set value in bits 12, 13, and 14.
Note 2. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
Note 3. In clock mode 0, the frequency of the EXTAL pin input clock or the crystal resonator.
In clock mode 1, the frequency of the USB_X1 pin input clock or the crystal resonator.
Caution: Do not use this LSI for frequency settings other than those in Table 6.3.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Clock I/O
Source Output
EXTAL/crystal CKIO
resonator
USB_X1/crystal CKIO
resonator
Ratio of Internal Clock
Frequencies
*2
(I : B : P1 : P0)
30 : 10 : 5 : 5/2
20 : 10 : 5 : 5/2
10 : 10 : 5 : 5/2
8 : 8/3 : 4/3 : 2/3
16/3 : 8/3 : 4/3 : 2/3
8/ 3 : 8/3 : 4/3 : 2/3
Divider 1
1
1/4
Selectable Frequency Range (MHz)
Output
Input Clock CPU Clock
*3
Clock (CKIO Pin) (Iφ)
10.00 to 50.00 to 300.00 to
13.33 66.67 400.00
200.00 to
266.67
100.00 to
133.33
48.00 64.00 384.00
256.00
128.00
6. Clock Pulse Generator
PLL Circuit CKIO Frequency
ON (x30) (EXTAL/crystal
resonator) x5
ON (x32) (USB_X1/crystal
resonator) x5
Internal Peripheral
Bus Clock Clock 1
(Bφ) (P1φ)
100.00 to 50.00 to
133.33 66.67
128.00 64.00
Peripheral
Clock 0
(P0φ)
25.00 to
33.33
32.00
6-5