Next Register Set Continuous Execution Setting - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
Start link address: 00001000H
Set the link mode
Figure 9.35 Setting Example 4
9.8.5

Next Register Set Continuous Execution Setting

The following figure shows the flowchart for executing DMA transfers continuously by using two Next Register Sets in
register mode. While a DMA transaction is being executed using one Next Register Set, the other Next Register Set is set
in order to continue to execute DMA transfers.
Slave Set N0
interface
Master
interface
Figure 9.36 Image of Next Register Set Continuous Execution
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Set 1 in the EN
(DMA transfer enable)
and STG bits
Set N1 Set N0
Load N0 Load N1
Transfer N0
Continue
The Next Register Set is set by the DMAEND interrupt
or status register polling
Start
(setting example 4)
DCTRL ← 00000001H
NXLA_0 ← 00001000
CHCFG_0 ← 80000000H
CHCTRL_0 ← 00000008H
CHCTRL_0 ← 00000005H
Link mode operation
End of link mode
Check CHSTAT_0
End
(setting example 4)
Set N1
Load N0 Load N1
Transfer N1 Transfer N0
Continue
9. Direct Memory Access Controller
⋅ Round robin
⋅ Clear the status
Check EN is set to "0"
Set N0
Transfer N1
Continue Continue
N0: Next0 Register Set
N1: Next1 Register Set
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