Timer Interrupt Skipping Set Register (Titcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.25

Timer Interrupt Skipping Set Register (TITCR)

TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt
skipping count. This module has one TITCR.
Bit Bit Name
7 T3AEN
6 to 4 3ACOR[2:0]
3 T4VEN
2 to 0 4VCOR[2:0]
Note: When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed. Before changing the
*
interrupt skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter (TITCNT).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit:
7 6
T3AEN 3ACOR[2:0]
Initial value:
0 0
R/W:
R/W R/W
Initial
value R/W Description
0 R/W T3AEN
Enables or disables TGIA_3 interrupt skipping.
0: TGIA_3 interrupt skipping disabled
1: TGIA_3 interrupt skipping enabled
000 R/W These bits specify the TGIA_3 interrupt skipping count within the range from 0 to
7.*
For details, see Table 10.38.
0 R/W T4VEN
Enables or disables TCIV_4 interrupt skipping.
0: TCIV_4 interrupt skipping disabled
1: TCIV_4 interrupt skipping enabled
000 R/W These bits specify the TCIV_4 interrupt skipping count within the range from 0 to
7.*
For details, see Table 10.39.
5 4 3 2 1
T4VEN 4VCOR[2:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
10. Multi-Function Timer Pulse Unit 2
0
0
R/W
10-55