Command Register (Spcmd) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.3.13

Command Register (SPCMD)

Each channel has four command registers (SPCMD0 to SPCMD3). SPCMD0 to SPCMD3 are used to set a transfer
format for master mode operation. Some of the bits in SPCMD0 are used to set a transfer mode for slave mode operation.
In master mode, this module sequentially references SPCMD0 to SPCMD3 according to the settings in bits SPSLN1 and
SPSLN0 in the sequence control register (SPSCR), and executes the serial transfer that is set in the referenced SPCMD.
While bit TEND in the status register (SPSR) indicates that transmission is not completed, correct operation of this
module cannot be guaranteed if SPCMD is changed that is referred by this module. SPCMD referenced by this module in
master mode can be checked by means of bits SPCP1 and SPCP0 in the sequence status register (SPSSR). When the
function of this module in slave mode is enabled, operation cannot be guaranteed if the value set in SPCMD0 is changed.
Bit Bit Name
15 SCKDEN
14 SLNDEN
13 SPNDEN
12 LSBF
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 15 14 13
SCK SLN SPN
DEN
DEN DEN
Initial value: 0 0 0
R/W: R/W R/W R/W
Bit: 7 6 5
⎯ ⎯
SSLKP
Initial value: 0 0 0
R/W:
R/W R R
Initial Value R/W Function
0 R/W RSPCK Delay Setting Enable
Sets the period from the point this module in master mode activates the
SSL signal until the RSPCK starts oscillation (RSPCK delay). If the
SCKDEN bit is 0, this module sets the RSPCK delay to 1 RSPCK. If the
SCKDEN bit is 1, this module starts the oscillation of RSPCK at an
RSPCK delay in compliance with the clock delay register (SPCKD)
settings.
To use this module in slave mode, the SCKDEN bit should be set to 0.
0: An RSPCK delay of 1 RSPCK
1: An RSPCK delay equal to SPCKD settings.
0 R/W SSL Negation Delay Setting Enable
Sets the period from the point this module in master mode stops RSPCK
oscillation until this module sets the SSL signal inactive (SSL negation
delay). If the SLNDEN bit is 0, this module sets the SSL negation delay to
1 RSPCK. If the SLNDEN bit is 1, this module negates the SSL signal at
an SSL negation delay in compliance with the slave select negation delay
register (SSLND) settings.
To use this module in slave mode, the SLNDEN bit should be set to 0.
0: An SSL negation delay of 1 RSPCK
1: An SSL negation delay equal to SSLND settings.
0 R/W Next-Access Delay Enable
Sets the period from the point this module in master mode terminates a
serial transfer and sets the SSL signal inactive until this module enables
the SSL signal assertion for the next access (next-access delay). If the
SPNDEN bit is 0, this module sets the next-access delay to 1 RSPCK +
2P1 φ . If the SPNDEN bit is 1, this module inserts a next-access delay in
compliance with the next-access delay register (SPND) settings.
To use this module in slave mode, the SPNDEN bit should be set to 0.
0: A next-access delay of 1 RSPCK + 2 P1 φ
1: A next-access delay equal to SPND settings.
0 R/W LSB First
Sets the data format in master mode or slave mode to MSB first or LSB
first.
0: MSB first
1: LSB first
16. Renesas Serial Peripheral Interface
12 11 10 9 8
LSBF SPB3 SPB2 SPB1 SPB0
0 0 1 1 1
R/W R/W R/W R/W R/W
4 3 2 1 0
⎯
BRDV1 BRDV0 CPOL CPHA
0 1 1 0 1
R R/W R/W R/W R/W
16-16