Status Register (Ssisr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.3.2

Status Register (SSISR)

SSISR consists of status flags indicating the operational status of this module and bits indicating the current channel
numbers and word numbers.
Bit:
31
-
Initial value:
UndefinedUndefined
R/W:
R
Bit: 15
-
Initial value:
UndefinedUndefinedUndefinedUndefined
R/W:
R
Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored.
Bit Bit Name
31, 30 ―
29 TUIRQ
28 TOIRQ
27 RUIRQ
26 ROIRQ
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- TUIRQ TOIRQ RUIRQ ROIRQ
0 0 0 0
R R/(W)* R/(W)* R/(W)* R/(W)*
14 13 12 11 10
- - - - -
UndefinedUndefinedUndefinedUndefinedUndefined
R R R R R
Initial Value R/W
Undefined R
0 R/(W)*
0 R/(W)*
0 R/(W)*
0 R/(W)*
25 24 23 22
IIRQ - - -
1
Undefined Undefined UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined
R R R R
9 8 7 6
- - - TCHNO[1:0]
0
R R R R
Description
Reserved
The read value is undefined. The write value should always be 0.
Transmit Underflow Error Interrupt Status Flag
This status flag indicates that transmit data was supplied at a lower rate than
was required.
This bit is set to 1 regardless of the value of the TUIEN bit and can be
cleared by writing 0 to this bit.
If TUIRQ = 1 and TUIEN = 1, an SSI interrupt occurs.
If TUIRQ = 1, SSITDR did not have data written to it before it was required
for transmission. This will lead to the same data being transmitted once
more and a potential corruption of multi-channel data. As a result, this
module will output erroneous data.
Note: When an underflow error occurs, the current data in the data buffer of
this module is transmitted until the next data is written.
Transmit Overflow Error Interrupt Status Flag
This status flag indicates that transmit data was supplied at a higher rate
than was required.
This bit is set to 1 regardless of the value of the TOIEN bit and can be
cleared by writing 0 to this bit.
If TOIRQ = 1 and TOIEN = 1, an SSI interrupt occurs.
If TOIRQ = 1, SSIFTDR had data written to it while the transmit FIFO is full
(TDC = H'8). This will lead to the loss of data and a potential corruption of
multi-channel data.
Receive Underflow Error Interrupt Status Flag
This status flag indicates that receive data was supplied at a lower rate than
was required.
This bit is set to 1 regardless of the value of the RUIEN bit and can be
cleared by writing 0 to this bit.
If RUIRQ = 1 and RUIEN = 1, an SSI interrupt occurs.
If RUIRQ = 1, SSIFRDR was read while the receive FIFO is empty (RDC =
H'0).This can cause invalid receive data to be stored, which may lead to
corruption of multi-channel data.
Receive Overflow Error Interrupt Status Flag
This status flag indicates that receive data was supplied at a higher rate than
was required.
This bit is set to 1 regardless of the value of the ROIEN bit and can be
cleared by writing 0 to this bit.
If ROIRQ = 1 and ROIEN = 1, an SSI interrupt occurs.
If ROIRQ = 1, SSIRDR was not read before there was new unread data
written to it. This will lead to the loss of data and a potential corruption of
multi-channel data.
Note: When an overflow error occurs, the current data in the data buffer of
this module is overwritten by the next incoming data from the SSI
interface.
19. Serial Sound Interface
21 20 19 18 17
- - - - -
R R R R R
5 4 3 2 1
TSWNO RCHNO[1:0] RSWNO IDST
0 1 0 0 1
R R R R R
16
-
R
0
1
R
19-10