Dma Error Interrupt; Interval Count Function - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.7.8

DMA Error Interrupt

If an error response is received for a DMA transfer or descriptor access, the DMAC regards it as an error and stops the
transfer. Upon receiving an error response, the EN bit of the CHSTAT_n register of transferring channel n is cleared to 0
and 1 is set in the ER bit (n = 0 to 15). Also, the DMA error interrupt is output.
The DMA error interrupt cannot be masked.
Once an error occurs, the data of the whole transfer cannot be guaranteed. Be sure to start the transaction again from the
beginning by following the procedure below.
1. Set 1 in the SWRST bit of the CHCTRL_n register.
2. Set each register again.
9.7.9

Interval Count Function

The interval at which a DMA transfer is executed can be adjusted by setting the ITVL bit of the channel interval register
(CHITVL_n). This function is intended to prevent the DMA controller from occupying the bus all the time.
When a read or write operation is completed, a countdown starts from the value set in CHITVL_n. The next internal
request is not executed until the count value reaches 0.
The following figure shows an example of how this works.
B φ
DMAREQ[0]
DMAREQ[1]
DMAACK[0]
DMAACK[1]
REQ0 internal request
REQ1 internal request
REQ0 internal request mask
REQ1 internal request mask
CHITVL0
CHITVL1
CH0 DMA Transfer
CH1 DMA Transfer
Figure 9.24 Interval Count
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
0 100 99
0 100 99 98 97
Write
Read
9. Direct Memory Access Controller
98 97 4 3 2 1
96 95 94 1 0
0
Write
Read
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