Tcnt_2 Write And Overflow/Underflow Contention In Cascade Connection - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.7.12

TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection

With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs during TCNT_1 count
(during a TCNT_2 overflow/underflow) in the T
and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a
compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel
0, TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input capture is selected
as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in Figure
10.107.
For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing.
P0φ
Address
Write signal
TCNT_2
TGRA_2 to
TGRB_2
Ch2 compare-
match signal A/B
TCNT_1 input
clock
TCNT_1
TGRA_1
Ch1 compare-
match signal A
TGRB_1
Ch1 input capture
signal B
TCNT_0
TGRA_0 to
TGRD_0
Ch0 input capture
signal A to D
Figure 10.107 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
state of the TCNT_2 write cycle, the write to TCNT_2 is conducted,
2
TCNT write cycle
T1 T2
TCNT_2 address
H'FFFE H'FFFF
TCNT_2 write data
H'FFFF
Disabled
M
M
N
P
Q
10. Multi-Function Timer Pulse Unit 2
N N + 1
M
P
10-147