Axi Bus Response Error Interrupt Control Register 2 (Axirerrctl2) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.10.8

AXI Bus Response Error Interrupt Control Register 2 (AXIRERRCTL2)

This register controls AXI bus response error interrupts.
Bit: 31
—
Initial value:
0
R/W:
R
Bit: 15
—
Initial value:
0
R/W:
R
Bit Bit Name
31 to 29 —
28 VDC501
RERREN
27 to 25 —
24 VDC502
RERREN
23 to 17 —
16 VDC504
RERREN
15 to 0 —
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
VDC501
— — — —
RERREN
0 0 0 0 0
R R R/W R R
14 13 12 11 10
— — — — —
0 0 0 0 0
R R R R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Response Error Interrupt Enable for Video Display Controller 5 IV1/3-BUS
Enables or disables interrupt requests when access from the IV1-BUS or IV3-BUS
of video display controller 5 generates a response error.
0: Interrupt requests are disabled.
1: Interrupt requests are enabled.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Response Error Interrupt Enable for Video Display Controller 5 IV5-BUS
Enables or disables interrupt requests when access from the IV5-BUS of video
display controller 5 generates a response error.
0: Interrupt requests are disabled.
1: Interrupt requests are enabled.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Response Error Interrupt Enable for Video Display Controller 5 IV6-BUS
Enables or disables interrupt requests when access from the IV6-BUS of video
display controller 5 generates a response error.
0: Interrupt requests are disabled.
1: Interrupt requests are enabled.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
25 24 23 22 21
VDC502
— — — —
RERREN
0 0 0 0 0
R R/W R R R
9 8 7 6 5
—
— — — —
0 0 0 0 0
R R R R R
5. LSI Internal Bus
20 19 18 17 16
VDC504
— — — —
RERREN
0 0 0 0 0
R R R R R/W
4 3 2 1 0
—
— — — —
0 0 0 0 0
R R R R R
5-21