Rscan0Rfists - Receive Fifo Buffer Interrupt Flag Status Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.40 RSCAN0RFISTS — Receive FIFO Buffer Interrupt Flag Status Register
Access: Can be read in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0244
Initial value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.54
Bit Position
31 to 8
7
6
5
4
3
2
1
0
The RSCAN0RFISTS register is cleared to 0000 0000
RFxIF Flag (x = 0 to 7)
The RFxIF flag is set to 1 when the RFIF flag in the RSCAN0RFSTSx register is set to 1 (a receive
FIFO interrupt request is present). When the RFIF flag is cleared to 0, the RFxIF flag is cleared to 0.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RSCAN0RFISTS register contents
Bit Name Function
Reserved These bits are always read as 0.
RF7IF Receive FIFO Buffer Interrupt Request Status Flag
RF6IF
RF5IF (x = 0 to 7)
RF4IF
RF3IF
RF2IF
RF1IF
RF0IF
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — RF7IF RF6IF
0 0 0 0
R R R R
0: No receive FIFO buffer x interrupt request is present.
1: A receive FIFO buffer x interrupt request is present.
in global reset mode.
H
21. CAN Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
RF5IF RF4IF RF3IF RF2IF
0 0 0 0
R R R R
17 16
— —
0 0
R R
1 0
RF1IF RF0IF
0 0
R R
21-84