Multi-Processor Serial Data Reception - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.4.2

Multi-Processor Serial Data Reception

Figure 15.15 and Figure 15.16 are sample flowcharts of multi-processor data reception. When the MPIE bit in SCR is
set to 1, reading the communication data is skipped until reception of the communication data in which the multi-
processor bit is set to 1. When the communication data in which the multi-processor bit is set to 1 is received, the
received data is transferred to RDR. During this time, the RXI interrupt request is generated. The other operations are the
same as the operations in asynchronous mode.
Figure 15.14 is the example of operation for reception.
Start bit
1
0
MPIE
RXI interrupt signal
RDR value
Start bit
1
0
MPIE
RXI interrupt signal
RDR value
Figure 15.14 Example of Reception (8-Bit Data/Multi-Processor Bit/One Stop Bit)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Data (ID1)
MPB
D0 D1 D7 1
MPIE = 0
RXI interrupt request
(multi-processor
interrupt) generated
(a) When the received ID does not match the ID of the receiving station itself
Data (ID2)
MPB
D0 D1 D7 1
ID1
RXI interrupt request
MPIE = 0
(multi-processor
interrupt) generated
(b) When the received ID matches the ID of the receiving station itself
Data (Data1)
Stop bit Start bit
1 0 D0 D1
RDR data read in RXI
MPIE bit set to 1 again
interrupt processing
when the received ID
routine
does not match the ID of
the receiving station itself
Data (Data2)
Stop bit Start bit
1 0 D0 D1
ID2
Since the received ID matches
RDR data read in RXI
the ID of the receiving station
interrupt processing
itself, reception continued and
routine
data received in RXI interrupt
processing routine
15. Serial Communications Interface
Stop bit
MPB
D7 0 1
Idle state
(mark state)
ID1
RXI interrupt request not
generated. RDR retains
the state.
MPB Stop bit
D7 0 1 Idle state
(mark state)
MPIE bit set to 1 again
1
1
Data2
15-36