Operation; Transfer Flow; Dma Transfer Requests - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.5

Operation

When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority
order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto
request, external request, and on-chip peripheral module request.
9.5.1

Transfer Flow

After the next source address register (N0SA_n/N1SA_n), next destination address register (N0DA_n/N1DA_n), next
transaction byte register (N0TB_n/N1TB_n), channel control register (CHCTRL_n), channel configuration register
(CHCFG_n), channel extension register (CHEXT_n), DMA control register (DCTRL_0_7/DCTRL_8_15), and DMA
extension resource selector (DMARS) are set for the target transfer conditions, the DMAC transfers data according to the
following procedure:
1. Checks to see if transfer is enabled (EN = 0 and TACT = 0 in channel status register).
2. Clears the channel status register (set 1 in the SWRST bit of the channel control register).
3. Enables DMA transfer (set 1 in the SETEN bit of the channel control register).
4. When a transfer request comes and transfer is enabled, the DMAC transfers one transfer unit of data (depending on
the DDS[3:0] and SDS[3:0] bit settings). For an auto request, the transfer begins automatically when 1 is set in the
STG bit of the channel control register. The CRTB_n value will be decremented by 1 for each transfer.
5. If 0 is set in the REN bit of the channel configuration register when transfer has been completed for the specified
count (when CRTB_n reaches 0), transfer ends normally. If the DEM bit of the channel configuration register is set
to 0 at this time, a DMA transfer end interrupt is sent to the CPU. If the REN bit is 1 when CRTB_n reaches 0,
transfer operations are continued with the values of N0SA_n/N1SA_n, N0DA_n/N1DA_n, and N0TB_n/N1TB_n
set by the RSEL bit of the channel configuration register until there are no more transfer requests.
6. When an address error in the DMAC is generated, the transfer is stopped. Transfers are also stopped when 1 is set in
the CLREN bit of CHCTRL_n.
9.5.2

DMA Transfer Requests

DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be
generated in external devices and on-chip peripheral modules that are neither the transfer source nor destination.
Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request.
External request or on-chip peripheral module request is selected by the DMARS0 to DMARS7 registers.
(1) Auto-Request Mode
When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer
between memory and an on-chip peripheral module unable to request a transfer, auto-request mode allows the DMAC to
automatically generate a transfer request signal internally. When the STG bit in channel control register is set to 1, the
transfer begins so long as the TACT bit in channel status register is 0.
(2) External Request Mode
In this mode a transfer is performed at the transfer request signal (DREQ0) of an external device of the LSI. When the
DMA transfer is enabled, DMA transfer is performed upon a DREQ input.
Choose to detect DREQ0 by either the edge or level of the signal input with the LVL, HIEN, and LOEN bits in channel
configuration register 0 as shown below. The source of the transfer request does not have to be the data transfer source or
destination.
For the output level settings of the DACK0 and TEND0 pins, refer to section 8, Bus State Controller.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
9. Direct Memory Access Controller
9-34