Receiver Module Data Transfer - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
23.9.3

Receiver Module Data Transfer

Once the module has left the idle state it is ready for data transfer. Data transfer timing can be achieved in three ways.
The transfer can be done by interrupts, or by polling the status register, or by DMA. There is a shared interrupt line
(transmit and receive) and a single receiver DMA request line. Data transfer for the receiver can be interrupted by error
signals caused by:
1. Clock recovery failure.
2. Transmission loss or interference – indicated by a preamble error.
3. Parity check failure.
Transmission loss or interference can cause the start of subframe or start of block preamble to be misplaced or not
present.
Parity check failure occurs when the parity bit is incorrect, this can be caused by any of the above.
• Clock Recovery Deviation
The receive margin for clock recovery is based on the following equation:
1
0.5 − − (L − 0.5) F −
M =
2N
where M = receive margin
N = oversampling rate
L = frame length = 33
D = duty cycle = 0.6
F = oversampling clock deviation = Level II accuracy = 1000 in 10e
Figure 23.7 indicates what the receive margin M represents.
Internal Clock
Data
Sampling Clock
Figure 23.7 Receive Margin
Introducing jitter into the equation gives the following inequality.
1
j ≤ 0.5 − − (L − 0.5) F −
2N
J = clock jitter
Eight times oversampling produces a receive margin = 39.25%
Four times oversampling produces a receive margin = 31.75%
Two times oversampling produces a receive margin = 16.75%
The fastest sample frequency is 48 kHz. This requires a clock speed of 128 × 48 kHz = 6.144 MHz. The worst case jitter
in one cycle is specified at 40 ns = 24.5% of the period. This means that an oversampling rate of 4 or more will satisfy the
inequality and therefore be sufficient for clock recovery.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
D − 0.5
(1 + F) × 100%
N
D − 0.5
(1 + F) × 100%
N
23. Renesas SPDIF Interface
–6
M
23-25