Loopback Mode; Interrupt Sources - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.4.10

Loopback Mode

When 1 is written to the SPLP bit in the pin control register (SPPCR), this module shuts off the path between the MISO
pin and the shift register, and between the MOSI pin and the shift register, and connects the input path and the output path
(reversed) of the shift register. This is called loopback mode. When a serial transfer is executed in loopback mode, the
transmit data becomes the received data. Figure 16.24 shows the configuration of the shift register input/output paths
for the case where this module in master mode is set in loopback mode.
Figure 16.24 Configuration of Shift Register Input/Output Paths in Loopback Mode (Master Mode)
16.4.11

Interrupt Sources

This module has interrupt sources of receive buffer full, transmit buffer empty, mode fault, and overrun. In addition, the
direct memory access controller can be activated by the receive buffer full or transmit buffer empty interrupt for data
transfer.
Table 16.11 shows the interrupt sources.
When any of the interrupt conditions in Table 16.11 is met, an interrupt is generated. The interrupt sources should be
cleared with data transfer by the CPU or direct memory access controller.
Table 16.11 Interrupt Sources
Name Interrupt Source
SPRI Receive buffer full
SPTI Transmit buffer empty
SPEI Mode fault
Overrun
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Shift Register
Selector
Normal Master
MOSI
Loopback Slave
Normal Master
MISO
Loopback Slave
Abbreviation Interrupt Condition
RXI (SPRIE = 1) • (SPRF = 1)
(SPTIE = 1) • (SPTEF = 1)
TXI
(SPEIE = 1) • (MODF = 1)
MOI
OVI (SPEIE = 1) • (OVRF = 1)
16. Renesas Serial Peripheral Interface
Normal
Loopback
Activation of Direct
Memory Access
Controller
Possible
Possible
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