Initial Settings For Transmitter Module; Transmitter Module Data Transfer - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
23.8.3

Initial Settings for Transmitter Module

When the TME bit is set to 1, the TUIR and CSTX bits are set to 1. After that, if data is written in the order of 1) TUI and
2) TLCS and TRCS, a channel status error will occur. To avoid this, be sure to write data in the order of 1) TLCS and
TRCS and 2) TUI.
Before writing the first audio data (write access to TLCA or TRCA by the CPU or write access to TDAD by the DMA
transfer) after setting the TME bit to 1, be sure to check that the CSTX and TUIR bits are cleared by writing to TLCS,
TRCS, and TUI.
23.8.4

Transmitter Module Data Transfer

Once the transmitter module has left the idle state, it is ready for data transfer. Data transfer timing can be achieved in
three ways. Either the transfer is done by interrupts, DMA requests or by polling the status register. There is a shared
interrupt line (for both transmit and receive) and a single transmitter DMA request line.
Figure 23.5 shows a data transfer with an interrupt for the transmitter.
Figure 23.5 Transmitter Data Transfer Flow Diagram - Interrupt Driven
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Start
Idle
Set control bit enabled
(TCBI)
Wait for interrupt
Load left or right audio
channel data
No
Enter idle state?
Yes
Set control bit disabled
(TCBI)
23. Renesas SPDIF Interface
23-22