Usage Notes; Timer Variation; Prohibition Against Setting H'ff To Wtcnt; Interval Timer Overflow Flag - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
12.5

Usage Notes

Pay attention to the following points when using this module in either the interval timer or watchdog timer mode.
12.5.1

Timer Variation

After timer operation has started, the period from the power-on reset point to the first count up timing of WTCNT varies
depending on the time period that is set by the TME bit of WTCSR. The shortest such time period is thus one cycle of the
peripheral clock, P0φ, while the longest is the result of frequency division according to the value in the CKS[2:0] bits.
The timing of subsequent incrementation is in accord with the selected frequency division ratio. Accordingly, this time
difference is referred to as timer variation.
This also applies to the timing of the first incrementation after WTCNT has been written to during timer operation.
12.5.2

Prohibition against Setting H'FF to WTCNT

When the value in WTCNT reaches H'FF, this module assumes that an overflow has occurred. Accordingly, when H'FF
is set in WTCNT, an interval timer interrupt or reset will occur immediately, regardless of the current clock selection by
the CKS[2:0] bits.
12.5.3

Interval Timer Overflow Flag

When the value in WTCNT is H'FF, the IOVF flag in WTCSR cannot be cleared.
Only clear the IOVF flag when the value in WTCNT has either become H'00 or been changed to a value other than H'FF.
12.5.4

System Reset by WDTOVF Signal

If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly.
Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To reset the entire system with
the WDTOVF signal, use the circuit shown in Figure 12.6.
Figure 12.6 Example of System Reset Circuit Using WDTOVF Signal
12.5.5

Internal Reset in Watchdog Timer Mode

When an internal reset is generated due to an overflow of the watchdog timer counter (WTCNT) in watchdog timer
mode, the watchdog reset control/status register (WRCSR) is not initialized, so the WOVF bit retains the value 1. As
long as the WOVF bit is 1, an internal reset will not be generated even if the WTCNT overflows again.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Reset input
(Low active)
Reset signal to
entire system
(Low active)
12. Watchdog Timer
RES
WDTOVF
12-10