Transmit Data Register (Ssitdr); Receive Data Register (Ssirdr) - Renesas RZ/A Series User Manual

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RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

Transmit Data Register (SSITDR)

SSITDR is a 32-bit register that stores data to be transmitted. The data for transmission to be stored to SSITDR is

automatically transferred from the transmit FIFO data register.

Data written to this register is transferred to the shift register upon transmission request. If the data word length is less

than 32 bits, the alignment is determined by the setting of the PDTA control bit in SSICR.

The CPU cannot read or write data from/to SSITDR.

Initial value:

Initial value:

SSIRDR is a 32-bit register that stores received data. The received data stored in SSIRDR is automatically transferred to

the receive FIFO data register.

Data in this register is transferred from the shift register each time data word is received. If the data word length is less

than 32 bits, the alignment is determined by the setting of the PDTA control bit in SSICR.

The CPU cannot read or write data from/to SSIRDR.

Initial value:

Initial value:

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

19. Serial Sound Interface

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