Reset Sync Pwm Mode Buffer Operation And Compare Match Flag - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.7.15

Reset Sync PWM Mode Buffer Operation and Compare Match Flag

When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin
will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1.
In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings
of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3.
At the same time, TGRC_4 functions as the buffer register for TGRA_4.
The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer
registers.
Figure 10.109 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and
BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0.
TGRB_3, TGRA_4,
TGRB_4
TGRD_3, TGRC_4,
TGRD_4
Figure 10.109 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
TGRA_3
TCNT_3
Point a
TGRC_3
Point b
H'0000
TIOC3A
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
TGFC
TGFD Not set
Buffer transfer with
compare match A3
Not set
10. Multi-Function Timer Pulse Unit 2
TGRA_3,
TGRC_3
TGRB_3, TGRD_3,
TGRA_4, TGRC_4,
TGRB_4, TGRD_4
10-149