Direct Memory Access Controller; Slave Area; Write Buffers - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
(2) Response unit (RRESP[1:0], BRESP[1:0])
OKAY is returned when RRESP[1:0] and BRESP[1:0] are 00 or 01.
ERROR is returned when RRESP[1:0] and BRESP[1:0] are 10 or 11.
(3) Protection unit information (ARPROT[2:0], AWPROT[2:0])
ARPROT[2], AWPROT[2]: Inverse of HPROT[0] (data/opcode)
ARPROT[1], AWPROT[1]: Fixed to 1 (non-secure access)
ARPROT[0], AWPROT[0]: Value of HPROT[1] (privileged)
(4) Atomic access (ARLOCK[1:0], AWLOCK[1:0])
ARLOCK[1:0], AWLOCK[1:0]: Fixed to 00 (normal access)
5.8.4

Direct Memory Access Controller

For details on the direct memory access controller, refer to section 9, Direct Memory Access Controller.
5.8.5

Slave Area

The control signals are handled as follows by the modules in the slave area.
(1) Cache control (ARCACHE[3:0], AWCACHE[3:0])
The L2 cache memory and write buffer refer to these signals. Other modules in the slave area do not refer to them.
(2) Response unit (RRESP[1:0], BRESP[1:0])
See Table 5.5, Address Map.
(3) Protection unit information (ARPROT[2:0], AWPROT[2:0])
ARPROT[2], AWPROT[2] (instruction/data): The modules in the slave area do not refer to these signals.
ARPROT[1], AWPROT[1] (non-secure/secure): The interrupt controller and L2 cache memory refer to these signals.
ARPROT[0], AWPROT[0] (privileged/user): The modules in the slave area do not refer to these signals.
(4) Atomic access (ARLOCK[1:0], AWLOCK[1:0])
This LSI does not support atomic access. Signals ARLOCK[1:0] and AWLOCK[1:0] should be fixed to 00 for normal
access by the bus master.*
Note: * This restriction means that instructions for exclusive access (LDREX, STREX, LDREXB, STREXB, LDREXD,
STREXD, LDREXH, STREXH) and semaphore instructions (SWP, SWPB) cannot be used by the Cortex-A9 in the
internal non-cacheable areas.
5.9

Write Buffers

A write buffer is provided at each connection between the north main bus and a peripheral bus and at each connection
between the media local bus and the north main bus, and CoreSight and the north main bus. When the AWCACHE[1:0]
cache control signals are set to cache-enabled or buffer-enabled (either of the AWCACHE[1:0] signals is set to 1), the
write buffer sends a write completion response to the bus master before accessing the slave area under the write buffer.
At this time, even if a slave error response is returned from the slave area to be accessed, it is ignored.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Other modules in the slave area do not refer to them.
5. LSI Internal Bus
5-13