Serial Bit Clock Control - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.4.8

Serial Bit Clock Control

This function is used to control and select the clock that is used for the serial bus interface.
If the serial bit clock direction is set to input (SCKD = 0), this module is in clock slave mode and the shift register uses
the bit clock that was input to the SSISCK pin.
If the serial bit clock direction is set to output (SCKD = 1), this module is in clock master mode, and the shift register
uses the oversampling clock or a divided oversampling clock as the bit clock. The oversampling clock is divided by the
ratio specified by the serial oversampling clock division ratio bits (CKDV) in SSICR for use as the bit clock by the shift
register.
In either case above, the output of the SSISCK pin is the same as the bit clock.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
19. Serial Sound Interface
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