Section 2 CPU
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
16 × 16-bit register-register divide: 20 states (MULXU.W), 21 states (MULXS.W)
32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
• CPU operating mode
• Advanced mode
• Power-down state
Transition to power-down state by the SLEEP instruction
CPU clock speed selection
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported by the H8S/2600 CPU only.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600
CPU only.
• The number of execution states of the MULXU and MULXS instructions;
Instruction
MULXU
MULXS
In addition, there are differences in address space, CCR and EXR register functions, and power-
down modes, etc., depending on the model.
Rev. 1.00 May 09, 2008 Page 30 of 954
REJ09B0462-0100
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, Erd
MULXS.B Rs, Rd
MULXS.W Rs, Erd
Execution States
H8S/2600
3
4
4
5
H8S/2000
12
20
13
21