Renesas H8S/2100 Series Hardware Manual page 534

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Section 17 I C Bus Interface (IIC)
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When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag is not
set at the end of a data transfer up to detection of a retransmission start condition or stop condition
after a slave address (SVA) or general call address match in I
Tables 17.5 and 17.6 show the relationship between the flags and the transfer states.
Table 17.5 Flags and Transfer States (Master Mode)
MST TRS BBSY ESTP
1 1 0 0
1 1 1↑ 0
1 — 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
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STOP IRTR AASX AL
0 0 0↓ 0
0 1↑ 0 0
0 — 0 0
0 — 0 0
0 1↑ 0 0
0 — 0 0
0 — 0 0
0 — 0 0
0 1↑ 0 0
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C bus format slave mode.
AAS ADZ ACKB ICDRF ICDRE State
0↓ 0↓ 0 —
0 0 0 —
0 0 — —
0 0 1↑ —
0 0 0 —
0 0 0 —
0 0 0 —
0 0 0 —
0 0 0 —
0 Idle state (flag
clearing
required)
1↑ Start condition
detected
— Wait state
— Transmission
end (ACKE=1
and ACKB=1)
1↑ Transmission
end with
ICDRE=0
0↓ ICDR write with
the above state
1 Transmission
end with
ICDRE=1
0↓ ICDR write with
the above state
or after start
condition
detected
1↑ Automatic data
transfer from
ICDRT to ICDRS
with the above
state