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Section 20 LPC Interface (LPC)
20.3.17 SERIRQ Control Register 4 (SIRQCR4)
SIRQCR4 is used to select the SERIRQ interrupt requests of the SCIF.
Initial
Bit
Bit Name
Value
7 to 4
All 0
3
SCSIRQ3
0
2
SCSIRQ2
0
1
SCSIRQ1
0
0
SCSIRQ0
0
Rev. 1.00 May 09, 2008 Page 624 of 954
REJ09B0462-0100
R/W
Slave Host Description
R/W
Reserved
The initial value should not be changed.
R/W
SCIF SERIRQ Request
R/W
These bits select host interrupt requests of the SCIF.
R/W
0000: No host interrupt request
R/W
0001: HIRQ1
0010: SMI
0011: HIRQ3
0100: HIRQ4
0101: HIRQ5
0110: HIRQ6
0111: HIRQ7
1000: HIRQ8
1001: HIRQ9
1010: HIRQ10
1011: HIRQ11
1100: HIRQ12
1101: HIRQ13
1110: HIRQ14
1111: HIRQ15
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