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Bit
Bit Name
1
CNTMD45A
0
CNTMD23A
9.3.5
PWM Prescaler Latch Register (PRELAT)
PRELAT is a shift register in PWMPRE. When one pulse is completed, the data of PWMPRE is
transferred to PRELAT automatically. This register cannot be accessed by the CPU directly.
Initial
Value
R/W
0
R/W
0
R/W
Section 9 8-Bit PWM Timer (PWMU)
Description
Channel 4 and 5, 16-bit Counter Select
0: Channel 4 and 5 are set to 8-bit count operating
mode
1: Channel 4 and 5 are set to 16-bit count operating
mode
When selecting 16-bit count operating mode, 12-bit
count mode must be non-selectable (CNTMD45B =
0). For details, see table 9.5.
Channel 2 and 3, 16-bit Counter Select
0: Channel 2 and 3 are set to 8-bit count operating
mode
1: Channel 2 and 3 are set to 16-bit count operating
mode
When selecting 16-bit count operating mode, 12-bit
count mode must be non-selectable (CNTMD23B =
0). For details, see table 9.4.
Rev. 1.00 May 09, 2008 Page 207 of 954
REJ09B0462-0100
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