Usage Notes; Input Clock Restrictions; Caution On Period Setting - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Usage Notes

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at

least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a

narrower pulse width. In phase counting mode, the phase difference and overlap between the two

input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure

10.43 shows the input clock conditions in phase counting mode.

Notes: Phase difference and overlap

Figure 10.43 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

When counter clearing by compare match is set, TCNT is cleared in the final state in which it

matches the TGR value (the point at which the count value matched by TCNT is updated).

Consequently, the actual counter frequency is given by the following formula:

Where f: Counter frequency

φ: Operating frequency

N: TGR set value

: 1.5 states or more

: 2.5 states or more

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 1.00 May 09, 2008 Page 283 of 954

REJ09B0462-0100