Renesas H8S/2100 Series Hardware Manual page 15

11.4 Operation ........................................................................................................................... 303
11.4.1 Timer Mode .......................................................................................................... 303
11.4.2 Cycle Measurement Mode .................................................................................... 305
11.5 Interrupt Sources................................................................................................................ 310
11.6 Usage Notes ....................................................................................................................... 311
11.6.1 Conflict between TCMCNT Write and Count-Up Operation............................... 311
11.6.2 Conflict between TCMMLCM Write and Compare Match.................................. 311
11.6.3 Conflict between TCMICR Read and Input Capture............................................ 312
11.6.4 Conflict between Edge Detection in Cycle Measurement Mode
and Writing to TCMMLCM or TCMMINCM...................................................... 312
11.6.5 Conflict between Edge Detection in Cycle Measurement Mode
and Clearing of TCMMDS Bit in TCMCR .......................................................... 313
11.6.6 Settings of TCMCKI and TCMMCI..................................................................... 313
11.6.7 Setting for Module Stop Mode ............................................................................. 313
Section 12 8-Bit Timer (TMR) ..........................................................................315
12.1 Features.............................................................................................................................. 315
12.2 Input/Output Pins............................................................................................................... 318
12.3 Register Descriptions ......................................................................................................... 319
12.3.1 Timer Counter (TCNT)......................................................................................... 321
12.3.2 Time Constant Register A (TCORA).................................................................... 321
12.3.3 Time Constant Register B (TCORB) .................................................................... 321
12.3.4 Timer Control Register (TCR).............................................................................. 322
12.3.5 Timer Control/Status Register (TCSR)................................................................. 326
12.3.6 Time Constant Register C (TCORC) .................................................................... 331
12.3.7 Input Capture Registers R and F (TICRR and TICRF)......................................... 331
12.3.8 Timer Connection Register I (TCONRI) .............................................................. 332
12.3.9 Timer Connection Register S (TCONRS) ............................................................ 332
12.3.10 Timer XY Control Register (TCRXY) ................................................................. 333
12.4 Operation ........................................................................................................................... 334
12.4.1 Pulse Output.......................................................................................................... 334
12.5 Operation Timing............................................................................................................... 335
12.5.1 TCNT Count Timing ............................................................................................ 335
12.5.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 336
12.5.3 Timing of Timer Output at Compare-Match......................................................... 336
12.5.4 Timing of Counter Clear at Compare-Match........................................................ 337
12.5.5 TCNT External Reset Timing............................................................................... 337
12.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 338
12.6 TMR_0 and TMR_1 Cascaded Connection....................................................................... 339
12.6.1 16-Bit Count Mode ............................................................................................... 339
Rev. 1.00 May 09, 2008 Page xv of xxvi