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4.3
Register Descriptions
This LSI has the following registers for resets.
Table 4.3
Register Configuration
Register Name
Reset status register
System control register
Timer control/status register_0
Timer control/status register_1
Note: * Data bus width in the upper cell: when writing
Data bus width in the lower cell: when reading
For access to the registers, see section 13, Watchdog Timer (WDT)
4.3.1
Reset Status Register (RSTSR)
RSTSR indicates the state of generating a pin reset/power-on reset.
Bit
Bit Name
7 to 1
0
PORF
Abbreviation
RSTSR
SYSCR
TCSR_0
TCSR_1
Initial
Value
R/W
Description
All 0
R/W
Reserved
These bits are always read as 0. The initial value should
not be changed.
0
R
Power-on reset flag
This flag indicates that a power-on reset is generated.
1: [Setting condition]
When a power-on reset is generated.
0: [Clearing conditions]
When a pin reset is generated.
Initial
R/W
Value
R/W
H'00
R/W
H'09
R/W
H'00
R/W
H'00
Rev. 1.00 May 09, 2008 Page 77 of 954
Section 4 Resets
Data Bus
Address
Width
H'FB35
8
H'FFC4
8
H'FFA8
16*
8
H'FFEA
16*
8
REJ09B0462-0100
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