C Bus Mode Register (Icmr) - Renesas H8S/2100 Series Hardware Manual

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Section 17 I C Bus Interface (IIC)
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17.3.4 I

C Bus Mode Register (ICMR)

ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Bit Bit Name
7 MLS
6 WAIT
5 CKS2
4 CKS1
3 CKS0
Rev. 1.00 May 09, 2008 Page 500 of 954
REJ09B0462-0100
Initial
Value R/W Description
0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
0 R/W Wait Insertion Bit
This bit is valid only in master mode with the I
format.
0: Data and the acknowledge bit are transferred
1: After the fall of the clock for the final data bit (8
For details, see section 17.4.7, IRIC Setting Timing and
SCL Control.
0 R/W Transfer Clock Select 2 to 0
0 R/W These bits are used only in master mode.
0 R/W These bits select the required transfer rate, together
with the IICX2 (IIC_2) and IICX0 (IIC_0) bits in STCR.
See table 17.4.
consecutively with no wait inserted.
clock), the IRIC flag is set to 1 in ICCR, and a wait
state begins (with SCL at the low level). When the
IRIC flag is cleared to 0 in ICCR, the wait ends and
the acknowledge bit is transferred.
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C bus format is used.
2
C bus
th