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This LSI incorporates the SPI flash memory serial interface (FSI) that supports the communication
between this LSI and SPI flash memory. The FSI performs communications using the LPC or
CPU of this LSI as a master.
21.1
Features
Figure 21.1 shows a block diagram of the FSI.
• Supports communications between this LSI and SPI flash memory.
• Can operate as a master.
• Transfer clock selectable from system clock or LCLK.
• Four interrupt sources: Transmit end, receive data full, and command and write receive
interrupts
• Direct transfer between LPC and SPI: Supports Read instruction, and Byte/Page-Program, and
AAI-Program instructions.
• LPC-SPI command transfer: Supports instructions other than above.
• Supports LPC/FW memory cycles of the LPC interface.
• Supports byte, word, and longword transfers of FW memory cycles.
• Provides independent LPC communication enable bits
• Supports LPC reset and LPC shut-down.
Section 21 FSI Interface
Section 21 FSI Interface
Rev. 1.00 May 09, 2008 Page 647 of 954
REJ09B0462-0100
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