Renesas H8S/2100 Series Hardware Manual page 654

Section 20 LPC Interface (LPC)
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than B'0000 in the slave's synchronization return cycle, but with the LPC of this LSI a
value of B'0000 always returns.
If the received address matches the host address in an LPC register (IDR, ODR, STR, and TWR),
the LPC interface enters the busy state; it returns to the idle state by output of a state count 12
turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle
forced termination (abort), registers and flags are not changed.
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 20.2 and 20.3.
Table 20.3 LPC I/O Cycle
State
Count Contents
1 Start
2 Cycle type/direction
3 Address 1
4 Address 2
5 Address 3
6 Address 4
7 Turnaround (recovery) Host
8 Turnaround
9 Synchronization
10 Data 1
11 Data 2
12 Turnaround (recovery) Slave
13 Turnaround
Rev. 1.00 May 09, 2008 Page 628 of 954
REJ09B0462-0100
I/O Read Cycle
Drive Value
Source (3 to 0)
Host 0000
Host 0000
Host Bits 15 to 12
Host Bits 11 to 8
Host Bits 7 to 4
Host Bits 3 to 0
1111
None ZZZZ
Slave 0000
Slave Bits 3 to 0
Slave Bits 7 to 4
1111
None ZZZZ
I/O Write Cycle
Contents
Start
Cycle type/direction
Address 1
Address 2
Address 3
Address 4
Data 1
Data 2
Turnaround (recovery) Host
Turnaround
Synchronization
Turnaround (recovery) Slave
Turnaround
Drive Value
Source (3 to 0)
Host 0000
Host 0010
Host Bits 15 to 12
Host Bits 11 to 8
Host Bits 7 to 4
Host Bits 3 to 0
Host Bits 3 to 0
Host Bits 7 to 4
1111
None ZZZZ
Slave 0000
1111
None ZZZZ