Initialization; Serial Data Transmission (Except In Block Transfer Mode) - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Section 14 Serial Communication Interface (SCI)

Initialization

Before starting transmitting and receiving data, initialize the SCI using the following procedure.

Initialization is also necessary before switching from transmission to reception and vice versa.

1. Clear the TE and RE bits in SCR to 0.

2. Clear the error flags ORER, ERS, and PER in SSR to 0.

3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set

the PE bit to 1.

4. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the SMIF bit is set to 1, the

TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high

impedance state.

5. Set the value corresponding to the bit rate in BRR.

6. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and

TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output

clock pulses.

7. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least 1 bit interval.

Setting prohibited the TE and RE bits to 1 simultaneously except for self diagnosis.

To switch from reception to transmission, first verify that reception has completed, and initialize

the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception

completion can be verified by reading the RDRF flag or PER and ORER flags. To switch from

transmission to reception, first verify that transmission has completed, and initialize the SCI. At

the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission

completion can be verified by reading the TEND flag.

Data transmission in smart card interface mode (except in block transfer mode) is different from

that in normal serial communication interface mode in that an error signal is sampled and data is

re-transmitted. Figure 14.26 shows the data re-transfer operation during transmission.

1. If an error signal from the receiving end is sampled after one frame of data has been

transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the

RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled.

2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is

re-transferred from TDR to TSR allowing automatic data retransmission.

Rev. 1.00 May 09, 2008 Page 412 of 954

REJ09B0462-0100