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Section 19 Keyboard Buffer Control Unit (PS2)
19.3.4
Keyboard Control Register L (KBCRL)
KBCRL enables the receive counter count and controls the keyboard buffer control unit pin
output.
Bit
Bit Name
7
KBE
6
KCLKO
5
KDO
4
—
Rev. 1.00 May 09, 2008 Page 562 of 954
REJ09B0462-0100
Initial
Value
R/W
Description
0
R/W
Keyboard Enable
Enables or disables loading of receive data into KBBR.
0: Loading of receive data into KBBR is disabled
1: Loading of receive data into KBBR is enabled
1
R/W
Keyboard Clock Out
Controls PS2 clock I/O pin output.
0: PS2 clock I/O pin is low
1: PS2 clock I/O pin is high
1
R/W
Keyboard Data Out
Controls PS2 data I/O pin output.
0: PS2 data I/O pin is low
1: PS2 data I/O pin is high
When the start bit (KDO) is automatically cleared
(KDO = 1) by means of automatic transmission, 0 is
written after reading 1.
1
—
Reserved
This bit is always read as 1 and cannot be modified.
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