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Section 21 FSI Interface
Bit
Bit Name
2 to 0 RBN2
RBN1
RBN0
21.3.4
FSI Instruction Register (FSIINS)
FSIINS sets an instruction to be sent to the SPI flash memory during command transfer. When
LFBUSY is 1, a write to this register by the EC (this LSI) is invalid. This register should not be set
in the processing other than FSICMDI and FSIWI interrupt processing.
Bit
Bit Name
7 to 0 bit 7 to bit 0 All 0
Rev. 1.00 May 09, 2008 Page 656 of 954
REJ09B0462-0100
R/W
Initial
Value
EC
Host Description
0
R/W
0
0
R/W
Initial
Value
EC
Host Description
R/W
Receive Byte Count 2-0
These bits specify the number of data bytes to be
received. After the FSI reception operation ends
(when FSIRXI in FSISTR is 1), the RBN value is
decremented (−1) each time FSIRDR is read. When
all the data bytes have been received, RBN is cleared
to B'000.
000: Receives no data
001: Receives one byte of data
010: Receives two bytes of data
011: Receives three bytes of data
100: Receives four bytes of data
101 to 111: Setting prohibited
If reception of five bytes or more is specified, FSIRDR
is overwritten.
These bits store an instruction to be transmitted to the
SPI flash memory.
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