Renesas H8S/2100 Series Hardware Manual page 565

6-bit single-chip microcomputer
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When WAIT = 1, and FS = 0 or FSX = 0 (I
SCL
8
SDA
8
IRIC
User processing
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
SCL
8
SDA
8
IRIC
User processing
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception.
Figure 17.19 IRIC Setting Timing and SCL Control (2)
When FS = 1 and FSX = 1 (clocked synchronous serial format)
SCL
7
SDA
7
IRIC
User processing
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
SCL
7
SDA
7
IRIC
User processing
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception.
Figure 17.20 IRIC Setting Timing and SCL Control (3)
2
C bus format, wait inserted)
9
A
Clear IRIC
Clear IRIC
9
A
Write to ICDR (transmit)
Clear IRIC
or read from ICDR (receive)
8
1
2
8
1
2
Clear IRIC
8
8
Clear IRIC
Section 17 I
1
2
3
1
2
3
1
1
3
4
3
4
1
1
Write to ICDR (transmit)
or read from ICDR (receive)
Rev. 1.00 May 09, 2008 Page 539 of 954
2
C Bus Interface (IIC)
Clear IRIC
Clear IRIC
REJ09B0462-0100

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