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• Host select register
Bits 5 to 3
Bits 15 to 3 in LADR1
Bits 15 to 3 in LADR1
Bits 15 to 3 in LADR1
Bits 15 to 3 in LADR1
Note:
When channel 1 is used, the content of LADR1 must be set so that the addresses for
*
channels 2, 3, 4, and SCIF are different.
20.3.6
LPC Channel 2 Address Registers H and L (LADR2H and LADR2L)
LADR2 sets the LPC channel 2 host address. The LADR2 contents must not be changed while
channel 2 is operating (while LPC2E is set to 1).
• LADR2H
Initial
Bit
Bit Name
Value
7
Bit 15
0
6
Bit 14
0
5
Bit 13
0
4
Bit 12
0
3
Bit 11
0
2
Bit 10
0
1
Bit 9
0
0
Bit 8
0
I/O Address
Bit 2
Bits 1 and 0
0
Bits 1 and 0 in LADR1
1
Bits 1 and 0 in LADR1
0
Bits 1 and 0 in LADR1
1
Bits 1 and 0 in LADR1
R/W
Slave Host Description
R/W
Channel 2 Address Bits 15 to 8
R/W
Set the LPC channel 2 host address.
R/W
R/W
R/W
R/W
R/W
R/W
Section 20 LPC Interface (LPC)
Transfer
Cycle
Host Select Register
I/O write
IDR1 write (data)
I/O write
IDR1 write (command)
I/O read
ODR1 read
I/O read
STR1 read
Rev. 1.00 May 09, 2008 Page 599 of 954
REJ09B0462-0100
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