Serial Data Transmission (Asynchronous Mode) - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer
Hide thumbs Also See for H8S/2100 Series:
Table of Contents

Advertisement

Section 14 Serial Communication Interface (SCI)
14.4.5

Serial Data Transmission (Asynchronous Mode)

Figure 14.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt
request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to
TDR before transmission of the current transmit data has finished, continuous transmission can
be enabled.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark
state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 14.7 shows a sample flowchart for transmission in asynchronous mode.
Start
1
bit
0
TDRE
TEND
TXI interrupt
request generated
Figure 14.6 Example of Operation in Transmission in Asynchronous Mode
Rev. 1.00 May 09, 2008 Page 388 of 954
REJ09B0462-0100
Data
Parity
bit
D0
D1
D7
0/1
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt service routine
1 frame
(Example with 8-Bit Data, Parity, One Stop Bit)
Stop
Start
Data
bit
bit
1
0
D0
D1
TXI interrupt
request generated
Parity
Stop
1
bit
bit
Idle state
D7
0/1
1
(mark state)
TEI interrupt
request generated

Advertisement

Table of Contents
loading

This manual is also suitable for:

H8s/2112r

Table of Contents