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Section 11 16-Bit Cycle Measurement Timer (TCM)
Initial
Bit
Bit Name
Value
2
MINUDIE
0
1
CMMS
0
0
0
Rev. 1.00 May 09, 2008 Page 302 of 954
REJ09B0462-0100
R/W
Description
R/W
Cycle Lower Limit Underflow Interrupt Enable
Enables or disables the issuing of the TUDI interrupt
requests when the MINUDF flag in TCMCSR is set to 1.
0: Disable interrupt requests by MINUDF
1: Enable interrupt requests by MINUDF
R/W
Cycle Measurement Mode Selection
Selects use of the TCMMCI signal in cycle measurement
mode.
0: The TCMMCI signal is not used (cycle measurement is
always performed).
1: The TCMMCI signal is used.
When MCICTL in TCMCSR is 0, cycle measurement is
performed only while TCMMCI is low. When MCICTL is 1,
cycle measurement is performed only while TCMMCI is
high.
Note: Change this bit when CST = 0 and TCMMDS = 0.
R
Reserved
This bit is always read as 0 and cannot be modified.
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