Table of Contents
Advertisement
Module/
Classification
Function
Watchdog timer Watchdog
timer
(WDT)
Serial interface
Serial
communic-
ation
interface
with FIFO
(SCIF)
Serial
communi-
cation
interface
(SCI)
Smart card/
SIM
2
High-
I
C bus
performance
interface
communication
(IIC)
SMBus 2.0
interface
(SMBUS)
Keyboard
buffer
control unit
(PS2)
LPC
interface
(LPC)
Description
•
8 bits × two channels (selectable from eight counter input
clocks)
•
Switchable between watchdog timer mode and interval timer
mode
•
One channel (asynchronous mode)
•
16-stage FIFO buffers for transmission and reception
•
Full-duplex communication capability
•
On-chip baud rate generator allows any bit rate to be selected.
•
Direct control from the LPC host
•
One channel (choice of asynchronous or clocked synchronous
serial communication mode)
•
Full-duplex communication capability
•
Selection of the desired bit rate and LSB-first or MSB-first
transfer
•
The SCI module supports a smart card (SIM) interface.
•
Two channels (one of two channels is switchable between input
pin and output pin.)
•
Capable of consecutive transmission and reception
•
Two types of communication formats
•
2
I
C bus format: addressing format with an acknowledge bit, for
master/slave operation
•
Clocked synchronous serial format: non-addressing format
without an acknowledge bit, for master operation only
•
Supports SMBus 2.0 interface
•
Shares the communication function with IIC_0
•
On-chip PEC (Packet Error Checking multiplier)
•
Two channels
•
Conforms to PS/2 interface specifications
•
Direct bus drive
•
Interrupt and error detection
•
Four channels
•
Serial transfer of cycle type, address, and data in
synchronization with the PCI clock
•
Supports LPC interface I/O read and I/O write cycles
•
Supports the shutdown function (LPCPD) of the LPC interface
Section 1 Overview
Rev. 1.00 May 09, 2008 Page 5 of 954
REJ09B0462-0100
Advertisement
Table of Contents
