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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.14 SCIF Control Register (SCIFCR)
SCIFCR controls SCIF operations, and is accessible only from the CPU.
Bit
Bit Name
7
SCIFOE1
6
SCIFOE0
5
4
OUT2LOOP
3
CKSEL1
2
CKSEL0
1
SCIFRST
0
REGRST
Rev. 1.00 May 09, 2008 Page 474 of 954
REJ09B0462-0100
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
These bits enable or disable PORT output of the
SCIF.
For details, see table 16.5.
Reserved
The initial value should not be modified.
Enables or disables interrupts during a loopback
test.
0: Interrupt enabled
1: Interrupt disabled
These bits select the clock (SCLK) to be input to
the baud rate generator.
00: LCLK divided by 18
01: System clock divided by 11
10: Reserved for LCLK (not selectable)
11: Reserved for system clock (not selectable)
Resets the baud rate generator, FRSR, and FTSR.
0: Normal operation
1: Reset
Resets registers (except SCIFCR) accessible from
the H8S CPU or LPC interface.
0: Normal operation
1: Reset
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