Fsi Address Registers H, M, And L (Fsiarh, Fsiarm, And Fsiarl) - Renesas H8S/2100 Series Hardware Manual

Bit Bit Name
4 FLDCT
3 FLWAIT 0
2 to 0 

21.3.18 FSI Address Registers H, M, and L (FSIARH, FSIARM, and FSIARL)

FSIAR stores an SPI flash memory address. If the host address matches FSIHBAR, the FSIAR
value is updated. FSIAR value is not updated by command access.
• FSIARH
Bit Bit Name
7 to 0 bit 23 to
bit 16
• FSIARM
Bit Bit Name
7 to 0 bit 15 to
bit 8
R/W
Initial
Value EC Host Description

0 R/W

R/W

All 0 R/W
R/W
Initial
Value EC Host Description

All 0 R
R/W
Initial
Value EC Host Description

All 0 R
FSI LPC Direct
Selects access mode in SPI flash memory write. For
details, see section 21.4.6, SPI Flash Memory Write
Operation Mode.
0: LPC-SPI indirect transfer
1: LPC-SPI direct transfer
FSI LPC Wait
Selects access mode in SPI flash memory write. For
details, see section 21.4.6, SPI Flash Memory Write
Operation Mode.
0: No wait cycle is inserted.
1: Wait cycles can be inserted.
Reserved
The initial value should not be modified.
These bits store bits [23:16] of the SPI flash memory
address.
These bits store bits [15:8] of the SPI flash memory
address.
Rev. 1.00 May 09, 2008 Page 667 of 954
Section 21 FSI Interface
REJ09B0462-0100