In case of reading more bytes than the number that has been received, (number of received bytes +
1) of data are always read out from the FIFO.
Reception of more than 8 bytes by the FIFO structure for this CIR module leads to an overrun.
When an overrun occurs, only values up to the 8th byte to have been received are read out in
response to the reading of more than 8 bytes.
15.4.3
Operation in Watch Mode
Initiate the transition to watch mode after making the below settings for the mode transition.
• Select the subclock (φ
• Enable the CIR header-detected interrupt.
For a transition from watch mode to high-speed mode, the CIR module generates an interrupt on
detection of a received header, in accord with the settings before the transition.
The module is released from watch mode when the interrupt is generated, and makes the transition
to the high- or medium-speed mode.
15.4.4
Switching between System Clock and Sub Clock
If the operating clock is switched from the system clock to the subclock (φ
module is operating, operation may not proceed correctly. To switch the operating clock, be sure
to stop the CIR module (by clearing the CIRE bit) beforehand.
) as the operating clock for the CIR module.
SUB
Section 15 CIR Interface
) while the CIR
SUB
Rev. 1.00 May 09, 2008 Page 447 of 954
REJ09B0462-0100