Renesas H8S/2100 Series Hardware Manual page 475

Table 15.5 shows sample settings for the noise canceler circuit.
Table 15.5 Sample Settings for Noise Canceler Circuit
CLK1 and
CLK0
φ
Setting
φ
10 MHz
SUB
FLTCK1 and
BRR FLTCK0
Setting Setting
H'80 Not divided
Divided by 2
Divided by 4
Divided by 8
CIR Number of Stages
Sampling of Noise Canceler
Clock Circuit
12.9 µs
0
1
2
3
4
25.8 µs
0
2
4
51.6 µs
0
2
4
103.2 µs
0
2
4
Rev. 1.00 May 09, 2008 Page 449 of 954
Section 15 CIR Interface
Width of
Noise
Cancellation
12.9 µs
25.8 µs
38.7 µs
51.6 µs
64.5 µs
25.8 µs
77.4 µs
129 µs
51.6 µs
154.8 µs
258 µs
103.2 µs
309.6 µs
516 µs
REJ09B0462-0100