Pwm Prescaler Registers 0 To 5 (Pwmpre0 To Pwmpre5) - Renesas H8S/2100 Series Hardware Manual

Table 9.5 Counter Operation of the Channel 4 and 5
CNTMD45A in CNTMD45B in
PWMMPCR PWMOUTCR
0 0
0 1
1 0
1 1
Note: When 12/16-bit counter is selected, single pulse mode must be selected.
9.3.7

PWM Prescaler Registers 0 to 5 (PWMPRE0 to PWMPRE5)

PWMPRE are 8-bit readable/writable registers used to set the PWM cycle. The initial value is
H'00.
When the PWMPRE value is n, the PWM cycle is calculated as follows.
(1) 8-Bit Single Pulse Mode
PWM cycle = [255 × (n + 1)] / internal clock frequency (0 ≤ n ≤ 255)
Resolution, PWM Conversion Period, and Carrier Frequency when φ = 20 MHz
Table 9.6
(8-Bit Counter Operation)
Internal Clock
Frequency Resolution
φ
50 ns
φ/2
100 ns
φ/4
200 ns
φ/8
400 ns
Counter Operation of the Channel 4 and 5
8-bit counter operation
12-bit counter operation
(higher order: channel 5, lower order: channel 4)
16-bit counter operation
(higher order: channel 5, lower order: channel 4)
Setting prohibited
PWM Conversion Period
Min. Max.
12.8 µs
3.3 ms
25.5 µs
6.5 ms
51.0 µs
13.1 ms
102.0 µs
26.1 ms
Section 9 8-Bit PWM Timer (PWMU)
Carrier Frequency
Single Pulse Mode
Min.
306.4 Hz
153.2 Hz
76.6 Hz
38.3 Hz
Rev. 1.00 May 09, 2008 Page 209 of 954
REJ09B0462-0100
Max.
78.4 kHz
39.2 kHz
19.6 kHz
9.8 kHz