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• HHMAX
Bit
Bit Name
15
FLT1
14
FLT0
13
FLTE
12
FLTCK1
11
FLTCK0
10
9 to 0
HHMAX9 to
HHMAX0
Initial
Value
R/W
Description
0
R/W
Number of Stages of Noise Canceler Circuit Select
0
R/W
00: The noise canceler circuit consists of one stage
01: The noise canceler circuit consists of two stages
10: The noise canceler circuit consists of three
11: The noise canceler circuit consists of four stages
0
R/W
Noise Canceler Circuit Enable
0: Disables the noise canceler circuit
1: Enables the noise canceler circuit
0
R/W
Division Ratio Select for Noise Canceler Circuit
Clock
0
R/W
Divides the frequency of the sampling clock for CIR
reception selected by BRR.
00: Not divided
01: Divided by 2
10: Divided by 4
11: Divided by 8
0
R/W
Reserved
The initial value should not be changed.
All 0
R/W
Specifies the maximum high-level period for a
header or repeat header and the maximum low-level
period for a stop.
stages
Rev. 1.00 May 09, 2008 Page 439 of 954
Section 15 CIR Interface
REJ09B0462-0100
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