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(3)
PC5/WUE13/TIOCB1/TCLKC
The pin function is switched as shown below according to the combination of the TPU channel 1
setting, the TPSC2 to TPSC0 bits in TCR_0 or TCR_2 of TPU, and the PC5DDR bit.
When the WUEMR13 bit in WUEMRA of the interrupt controller is cleared to 0, this pin
functions as the WUE13 input pin.
TPU channel 1 setting
PC5DDR
Pin function
Notes: 1. This pin functions as the TCLKC input pin when the TPSC2 to TPSC0 bits in TCR_0 or
TCR_2 are B'110. Also, when channel 1 is set to phase counting mode, this pin
functions as the TCLKC input pin.
2. This pin functions as the TIOCB1 input pin when the TPU channel 1 timer is set to
normal operation mode, or to phase counting mode while the IOB3 to IOB0 bits in
TIOR_1 are set to B'10xx. (x: Don't care)
(4)
PC4/WUE12/TIOCA1
The pin function is switched as shown below according to the combination of the TPU channel 1
setting and the PC4DDR bit.
When the WUEMR12 bit in WUEMRA of the interrupt controller is cleared to 0, this pin
functions as the WUE12 input pin.
TPU channel 1 setting
PC4DDR
Pin function
Note:
This pin functions as the TIOCA1 input pin when the TPU channel 1 timer is set to
*
normal operation mode, or to phase counting mode while the IOA3 to IOA0 bits in
TIOR_1 are set to B'10xx. (x: Don't care)
Input setting or initial value
0
PC5 input pin
TIOCB1 input pin*
WUE13 input pin/TCLKC input pin*
Input setting or initial value
0
PC4 input pin
TIOCA1 input pin*
1
PC5 output pin
2
1
PC4 output pin
WUE12 input pin
Rev. 1.00 May 09, 2008 Page 181 of 954
Section 8 I/O Ports
Output setting
TIOCB1 output pin
1
Output setting
TIOCA1 output pin
REJ09B0462-0100
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