Interrupt Enable Register (Ceir) - Renesas H8S/2100 Series Hardware Manual

Section 15 CIR Interface
15.3.4

Interrupt Enable Register (CEIR)

CEIR consists of the bits that enable/disable various interrupts.
Bit Bit Name

7, 6
5 REPIE
4 OVEIE
3 RENDIE
2 ABIE
1 FREIE
0 HEADFIE
Rev. 1.00 May 09, 2008 Page 436 of 954
REJ09B0462-0100
Initial
Value R/W Description
All 0 R/W Reserved
The initial value should not be changed.
0 R/W Repeat Detection Interrupt Enable
0: REPI interrupt request is disabled.
1: REPI interrupt request is enabled.
0 R/W Overrun Error Interrupt Enable
0: OVEI interrupt request is disabled.
1: OVEI interrupt request is enabled.
0 R/W Receive End Interrupt Enable
0: RENDI interrupt request is disabled.
1: RENDI interrupt request is enabled.
0 R/W Abort Interrupt Enable
0: ABI interrupt request is disabled.
1: ABI interrupt request is enabled.
0 R/W Framing Error Interrupt Enable
0: FREI interrupt request is disabled.
1: FREI interrupt request is enabled.
0 R/W Header Detection Interrupt Enable
0: HEADFI interrupt request is disabled.
1: HEADFI interrupt request is enabled.