Renesas H8S/2100 Series Hardware Manual page 661

Table 20.7 Scope of Initialization in Each LPC interface Mode
Items Initialized
LPC transfer cycle sequencer (internal state), LPCBSY and ABRT
flags
SERIRQ transfer cycle sequencer (internal state), CLKREQ and
IRQBSY flags
LPC interface flags
(IBF1, IBF2, IBF3A, IBF3B, IBF4, MWMF, C/D1, C/D2, C/D3, C/D4,
OBF1, OBF2, OBF3A, OBF3B, OBF4, SWMF, DBU), GA20 (internal
state)
Host interrupt enable bits
(IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B,
SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3, SELREQ, SMIE4, IRQ6E4,
IRQ9E4 to IRQ11E4, IEDIR2 to IEDIR4), Q/C flag
LRST flag
SDWN flag
LRSTB bit
SDWNB bit
SDWNE bit
LPC interface operation control bits
(LPC4E to LPC1E, FGA20E, LADR1 to LADR4, IBFIE1 to IBFIE4,
PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB, TWRE, SELSTR3,
SELIRQ1, SELSMI, SELIRQ3 to SELIRQ15, OBEIE, SCIFE, IDR1 to
IDR4, ODR1 to ODR4, TWR0 to TWR15, SCSIRQ0 to SCSIRQ3,
and SCIFADRH/L)
LRESET signal
LPCPD signal
LAD3 to LAD0, LFRAME, LCLK, SERIRQ, CLKRUN signals
PME, LSMI, LSCI, GA20 signals (when function is selected)
PME, LSMI, LSCI, GA20 signals (when function is not selected)
Note: System reset: Reset by RES pin input, power-on reset or WDT overflow
LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR)
LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS)
Section 20 LPC Interface (LPC)
System
Reset LPC Reset
Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized Initialized
Initialized (0) Can be
set/cleared
Initialized (0) Initialized (0) Can be
Initialized (0) HR: 0
SR: 1
Initialized (0) Initialized (0) HS: 0
Initialized (0) Initialized (0) HS: 1
Initialized Retained
Input (port Input
function)
Input
Input
Output
Port function Port function
Rev. 1.00 May 09, 2008 Page 635 of 954
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LPC
Shutdown
Initialized
Initialized
Retained
Retained
Can be
set/cleared
set/cleared
0 (can be
set)
SS: 1
SS: 0 or 1
Retained
Input
Input
Hi-Z
Hi-Z