Renesas H8S/2100 Series Hardware Manual page 616

6-bit single-chip microcomputer
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Section 20 LPC Interface (LPC)
• HICR1
Initial
Value
Bit
Bit Name
7
LPCBSY
0
Rev. 1.00 May 09, 2008 Page 590 of 954
REJ09B0462-0100
R/W
Slave Host Description
R
LPC Busy
Indicates that the LPC interface is processing a
transfer cycle.
0: LPC interface is in transfer cycle wait state
Bus idle, or transfer cycle not subject to processing
is in progress
Cycle type or address indeterminate during transfer
cycle
[Clearing conditions]
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software
shutdown
Forced termination (abort) of transfer cycle subject
to processing
Normal termination of transfer cycle subject to
processing
1: LPC interface is performing transfer cycle
processing
[Setting condition]
Match of cycle type and address

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