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Register Name
Port G Nch-OD control register
Port H Nch-OD control register
Port G noise canceler enable
register
Port G noise canceler decision
control register
Port G noise cancel cycle setting
register
Receive control register 1
Receive control register 2
Receive status register
Interrupt enable register
Bit rate register
Receive data register 0 to 7
Header minimum high-level period
register
Header maximum high-level period
register
Header minimum low-level period
register
Header maximum low-level period
register
Data level 0 minimum period
register
Data level 0 maximum period
register
Data level 1 minimum period
register
Data level 1 maximum period
register
Repeat header minimum low-level
period register
Number
Abbreviation
of bits
PGNOCR
8
PHNOCR
8
PGNCE
8
PGNCMC
8
PGNCCS
8
CCR1
8
CCR2
8
CSTR
8
CEIR
8
BRR
8
CIRRDR0 to
8
CIRRDR7
HHMIN
16
HHMAX
16
HLMIN
8
HLMAX
8
DT0MIN
8
DT0MAX
8
DT1MIN
8
DT1MAX
8
RMIN
8
Section 27 List of Registers
Address
Module
H'F988
PORT
(PORTS = 1)
H'F989
PORT
(PORTS = 1)
H'F98A
PORT
(PORTS = 1)
H'F98C
PORT
(PORTS = 1)
H'F98E
PORT
(PORTS = 1)
H'FA40
CIR
H'FA41
CIR
H'FA42
CIR
H'FA43
CIR
H'FA44
CIR
H'FA45
CIR
H'FA48
CIR
H'FA46
CIR
H'FA4B
CIR
H'FA4A
CIR
H'FA4C
CIR
H'FA4D
CIR
H'FA4E
CIR
H'FA4F
CIR
H'FA50
CIR
Rev. 1.00 May 09, 2008 Page 831 of 954
Data
Access
Width
States
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
REJ09B0462-0100
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