Renesas H8S/2100 Series Hardware Manual page 704

6-bit single-chip microcomputer

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Table of Contents

Section 21 FSI Interface

FSIWDR[31:0]

FSICR2 TE bit

FSISTR OBF bit

FSICK (CPOS = CPHS =0)

Figure 21.7 AAI-Program Instruction Execution Timing

Read Instructions

If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is cleared to 0, the SPI

flash memory address is stored in FSIAR. Then, the SPI flash memory address and the instruction

which is stored in FSIRDINS in advance are transferred to FSITDR. After SYNC (long wait) has

been returned, the RE bit in FSICR2 is set, and Read instruction execution starts. The read data is

then received and stored in FSIRDR. When the reception has been completed, SYNC (Ready),

read data, and TAR are returned to the host. Figure 21.8 shows an example of data transfer to

FSIRDR. Figure 21.9 shows the Read instruction execution timing.

Rev. 1.00 May 09, 2008 Page 678 of 954

REJ09B0462-0100

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