Renesas H8S/2100 Series Hardware Manual page 168

Section 6 Interrupt Controller
(1) Program area in on-chip memory, 1-state execution instruction at specified break address
φ
Address bus
Break request
signal
(2) Program area in on-chip memory, 2-state execution instruction at specified break address
φ
Address bus
Break request
signal
H'0310 NOP
H'0312 MOV.W #xx : 16,Rd
H'0314 NOP
H'0316 NOP
(3) Program area in external memory (2-state access, 16-bit-bus access), 1-state execution instruction
at specified break address (Not available in this LSI)
φ
Address bus
Break request
signal
Rev. 1.00 May 09, 2008 Page 142 of 954
REJ09B0462-0100
Instruction Instruction Instruction Instruction
fetch fetch fetch fetch
H'0310 H'0312 H'0314 H'0316
NOP NOP NOP
execution execution execution
H'0310 NOP
H'0312 NOP
Breakpoint NOP instruction is executed at breakpoint address H'0312 and
H'0314 NOP
H'0316 NOP
Instruction Instruction Instruction Instruction
fetch fetch fetch fetch
H'0310 H'0312 H'0314 H'0316
NOP MOV.W
execution execution
Breakpoint MOV instruction is executed at breakpoint address H'0312,
Instruction Instruction
fetch fetch
H'0310 H'0312
NOP
execution
H'0310 NOP
H'0312 NOP
Breakpoint NOP instruction at breakpoint address H'0312 is not executed;
H'0314 NOP
H'0316 NOP
Figure 6.12 Examples of Address Break Timing
Instruction Internal
fetch operation
Stack save
H'0318 SP-2 SP-4
Interrupt exeption handling
next address, H'0314; fetch from address H'0316 starts after
end of exception handling.
Instruction Internal
fetch operation
Stack save
H'0318 SP-2 SP-4
Interrupt exeption handling
NOP instruction at next address, H'0316, is not executed;
fetch from address H'0316 starts after end of exception handling.
Instruction Internal
fetch operation
Stack save
H'0314 SP-2
Interrupt exeption handling
fetch from address H'0312 starts after end of exception handling.
Vector Internal Instruction
fetch operation fetch
H'0036
Vector Internal Instruction
fetch operation fetch
H'0036
Vector Internal
fetch operation
SP-4 H'0036